The general problem to which this invention is addressed is the improvement in performance and reliability of the SOI MOSFET, which is the active element common to many microelectronic circuits. A conventional MOSFET operates by driving current through the channel region between the source and drain of the device. The conductivity of the channel region is modulated by the application of a voltage on the conducting gate above the channel surface and insulated from it. Efforts are ongoing within many MOS integrated circuit manufacturing companies as well as at many universities and government laboratories to improve the speed and available drive current of the SOI MOSFET, to reduce its power consumption, and to improve its reliability and radiation hardness for applications in harsh or remote environments, including space.
Silicon-on-insulator (SOI) is the generic term describing those technologies in which the MOSFETs or other active devices are built in a thin film of silicon over an insulating layer or substrate. The presence of the insulator reduces the parasitic capacitances in the MOSFET compared to a bulk silicon device, resulting in inherent improvements in the speed and power dissipation of MOS integrated circuits, as well as improved immunity to single-event upset of MOS memory elements in a radiation environment. However, the presence of the back interface in the SOI MOSFET can lead to failure of the integrated circuit in a radiation environment caused by charging of the silicon/insulator interface by radiation-induced interface states or fixed charges at this interface (D. C. Mayer, Modes of Operation and Radiation Sensitivity of Ultrathin SOI Transistors, IEEE Trans. Electron Devices, 37, 1280, 1990).
The SOI gate-all-around (GAA) MOSFET, has been described and fabricated to improve the performance of the SOI MOSFET. (D. Hisamoto et al., A Fully Depleted Lean-Channel Transistor (DELTA)--A Novel Vertical Ultra Thin SOI MOSFET, IEDM Tech. Digest, 833 (1989), and J. P. Colinge et al., Silicon-on-Insulator Gate-All-Around Device, IEDM Tech. Digest, 595, 1990). By placing an active gate at the bottom of the SOI device, this bottom active gate creates an enlarged channel of the MOSFET and thereby contributes to the drive current by adding a back surface current to the device front surface current created by the top active gate. Furthermore, by removing the back interface as a potential parasitic failure site in the device, the SOI GAA MOSFET has also demonstrated improved radiation hardness (R. K. Lawrence and H. L. Hughes, Radiation Effects in Gate-All-Around Structures, 1991 IEEE International SOI Conf. Proc., 80, 1991).
In previous methods of fabricating the SOI GAAMOSFET, the process required etching a tunnel beneath a SOI island, oxidizing the bottom of the island, and refilling the tunnel with polysilicon gate material. These procedures are not standard in MOSFET processing and are difficult to implement and control. This prior technique also leaves a very thin oxide layer between the bottom polysilicon gate and the wafer substrate, which increases the capacitive coupling between the bottom gate and the substrate. The capacitive coupling can reduce the speed of the device and create a reliability problem associated with degradation of the thin oxide. Additionally, in the conventional GAA process, the bottom surface of the mesa is defined and delineated by the Separation by Implanted Oxygen (SIMOX) process which uses an energetic oxygen implant and high-temperature anneal (K. Izumi et al., CMOS Devices Fabricated on Buried SiO.sub.2 Layers Formed by Oxygen Implantation into Silicon, Electronics Letts. 14, 593, 1978). This method of creating an oxide/silicon interface is known to generate a higher number of defects at the interface than would a conventional thermal oxidation, (S. Visitserngtrakul et al., Formation of Multiply Faulted Defects in Oxygen Implanted Silicon-on-Insulator Material, J. Appl. Phys. 69, 1784 1991). These residual defects can degrade the quality and reliability of the subsequent bottom gate oxide in the conventional GAA process.
Well known SOI processes, such as SIMOX and BESOI wafer processing, bonding and layer etching techniques are available, but have not been used to form GAA MOSFET devices. Such processes, as described for example in R. C. Frye et al., "A Field Assisted Bonding Process for Silicon Dielectric Isolation," J. Electrochem. Soc. 133, 1673 (1986), J. B. Lasky et al., "Silicon-on-Insulator by Bonding and Etch-Back," IEDM Tech. Digest, 684 (1985), W. P. Maszara et al., "Bonding of Silicon Wafers for Silicon-on-Insulator," J. Appl. Phys. 64, 4943 1988, and Q. Y. Tong and U. Gosele, "VLSI SOI Fabrication by SIMOX Wafer Bonding (SWB)", presented at 1992 IEEE International SOI Conference, Ponte Vedra Beach, Fla., October 1992, can be used to form SOI MOSFETs and can be used to form some of the structural components of GAA MOSFETs, but cannot by themselves form GAA MOSFETs. Thus, prior methods of forming SOI GAA MOSFETs involved etching a cavity in the buried oxide under the bottom of the MOSFET, oxidizing the bottom of the device, and filling the cavity with polysilicon to form the bottom gate. These techniques are difficult to control and prevent the GAA device from being formed by conventional MOS fabrication methods. These and other disadvantages are solved or reduced using the present invention.